FIG. 1 illustrates a prior art processor node 100 of a computer network. The processor node includes a circuit control module 111 and a plurality of dedicated combinations 120, 130, 140 of device drivers 121, 131 and 141 and device objects 122, 132 and 142 respectvely. The dedicated combinations 120, 130 and 140 enable data exchange between the circuit control module 111 and each of the devices 171, 172 and 173 respectively.
The elements of the dedicated combinations are interface unit specific, that is the device objects (interface objects) are specifically dedicated (e.g. preprogrammed, hard-wired) to interface with a certain type of device drivers and ultimately certain type of devices. The output and the input data of the device object with respect to the circuit control module 111 are however in generic form. The output and input data of the devise object with respect to the device driver is not generic and is device specific. In FIG. 1, the devices for illustration purposes are fiber optic line 170, modem 171, and T1 172 connections. The device driver 121 and the device object 122 used to drive the fiber optic device 170, is not capable of driving the modem device 171. Since each device and device driver of the prior art processor is type specific, the interface object or device object is specifically tailored to translate information from the particular disparate source (i.e. the device driver) into generic information that is usable in the circuit control module 111.
Similarly in FIG. 2, a prior art processor node 200 of a computer network includes a circuit control module 211 and a plurality of dedicated combinations 220, 230, 240 of device drivers 221, 231 and 241 and device objects 222, 232 and 242 respectively. In addition the device objects 222, 232 and 242 are operable connected to data tables 223, 233 and 243 respectively. The data tables are relational databases enabling information exchange. The dedicated combinations 220, 230 and 240 enable data exchange between the circuit control module 111 and each of the devices 271, 272 and 273 respectively. Similarly the elements of the dedicated combinations are interface unit specific, that is the device objects 222, 232 and 242 (interface objects) are specifically dedicated (e.g. preprogrammed, pre-wired) to interface with a certain type of device drivers and ultimately certain type of devices.
Likewise performance monitoring of the devices 170, 171, and 172 is necessarily device specific and not conducive to distributed monitoring functions. In the prior art processor node 100, the circuit control module 111 is a circuit state machine with data driven performance monitoring and archive. The storage capacity of the archive as it is contained within the node 100 is limited and thus its memory is constantly reused. The processor node in FIG. 2 may also include a supplemental archive 250, however this memory is equally limited due to space and configuration factors. The data in the archive 250 is also limited to used in the single processor node 200. Monitoring statistics such a report period, functions and alarms all must be incorporated into the circuit control module 111. Substitution of device 170 requires a new dedicated combination 120 of device driver 121 and device object 122. Initialization, monitoring, reporting and detecting functions are required for network performance monitoring. These functions are unfortunately done differently based on the type of device the device driver connects to. Therefore, depending on the characteristics of the device, the circuit control module 111 may need to be re-coded or changed which is labor intensive.
The prior art processors do not allow dynamic performance monitoring scheduling, or allow for persistent storage of performance data, and a single processor only supports the monitoring. For these and other reasons, there is a need for reducing commonality down to the device driver level, allowing for distributed gathering of performance monitoring records, generic performance monitoring records, distributed scheduling, performance monitoring across redundant processor nodes and incorporating device programming and control into same agent.